As memory cells, and particularly dynamic, random access memory (DRAM) cells, become increasingly smaller, charge storage becomes more difficult. Smaller cells include smaller capacitors, which in turn store less charge. Eventually, circuit noise can overcome the stored charge, making the data from the memory cells unreliable.
Several techniques have been used in the art to increase capacitance and charge storage without affecting, or while minimally affecting, cell size.
One such technique includes the use of trench capacitors, wherein capacitor plates are formed on the walls of trenches extending into the semiconductor substrate. Such trench capacitors use the area on the vertical walls of the trenches to increase the capacitance without increasing the size, or footprint, of the cells on the substrate (see for example, W. P. Noble et al., IEDM 1987, pp. 340-343).
The formation of capacitors on raised mesas can be used to accomplish the same results as trench capacitors (see for example, H. Arima et al., IEDM 1991, pp. 651-654).
Another technique, analogous to that of trench and mesa capacitors, is stacked capacitors. In a stacked capacitor environment, the capacitor plates are stacked over the cells, again increasing capacitance and charge storage with minimal or no increase in footprint. See, for example, JA 0278060 by Fujitsu showing a stacked capacitor structure.
JA 283860 by Mitsubishi Electric Corp. shows the formation of a conical structure within a capacitor trench. The capacitor plates are formed over the cone thereby increasing the area of the plates. This structure can achieve a modest increase in capacitor area (i.e. about 2.times.), but its reproducability is highly dependent on the etching steps used to form the cone. In addition, in practice, as trench widths become smaller (e.g., less than 0.8 .mu.m), the formation of such cones inside a trench becomes very difficult. Typically the chemical vapor deposition (CVD) of polysilicon (polycrystalline silicon) is a very conformal process and thus is not suitable forming such cones. Silicon cones may be formed inside a trench by sputtering processes provided the trench is sufficiently wide (e.g.,&gt;1.0 .mu.m). For smaller trench widths, the sputtered silicon tends substantially close the opening at the top of the trench, thus making cone formation difficult or impossible.
U.S. Pat. No. 4,906,590 to Kanetaki et al. shows a method of forming a trench capacitor wherein photoresist deposited within the trench is exposed to a standing wave of light intensity. The exposed photoresist developed to leave a patterned mask, which is in turn used to etch periodic hollows in the side wall of the trench. A capacitor plate is formed in the trench, the roughened side wall increasing the plate area.
U.S. Pat. No. 4,397,075 to Fatula, Jr. et al. (assigned to the assignee of the present invention) shows a method of forming an FET memory cell wherein a wet etch is used to form a widened well within a trench. The cell capacitor thus has an increased area relative to a capacitor formed within an unmodified trench.
To further address the problem of charge storage in increasingly smaller capacitors, it has been proposed to texture the capacitor plates, whereby to increase the charge storage area. Hayashide, Y., et al., "Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode," Extended Abstracts of the 22nd Conference on Solid State Devices and Materials, Sendai, 1990, pgs. 869-872, shows a method of forming polysilicon films on substrates wherein highly textured surfaces result. The Hayashide process is performed using low pressure, chemical vapor deposition (LPCVD) at a temperature of 580 degrees centigrade.
Watanabe, H., et al., "A New Stacked Capacitor Structure Using Hemispherical-Grain (HSG) Poly-Silicon Electrodes," Extended Abstracts of the 22nd Conference on Solid State Devices and Materials, Sendai, 1990, pgs. 873-876 shows a 64Mbit DRAM storage cell including roughened polysilicon storage electrodes formed by LPCVD at 600 degrees centigrade.
Hayashide and Watanabe both suffer from the disadvantage of being highly temperature dependent, bringing into question process reproducability.
In summary, while the problem of providing sufficient charge storage for increasingly smaller memory cells has been recognized in the art, the previously known solutions suffer from significant drawbacks. Trench, stacked, and mesa capacitor structures do not provide sufficient capacitor area for the increasingly smaller physical size and higher capacity memory cells. Processes which alter the shape of the trench (i.e. by providing wells or hollows) require significant additional processing to provide relatively small increases in capacitor area. The use of textured surfaces, as currently proposed, requires strict process tolerances which can, in turn, create difficulties in uniformly reproducing capacitor area. For example, the formation of a textured polysilicon surface must generally be accomplished in a narrow temperature range (e.g. 570.degree. C.-590.degree. C.). Thus subsequent process options are limited to lower temperatures, since subsequent higher process temperatures may reduce surface roughness.